VTS 2008 - Call for Papers

CALL FOR PAPERS

Scope -- Author Information -- Deadlines -- Additional Information Contacts -- Committees

Scope

The IEEE VLSI Test Symposium (VTS) explores emerging trends and novel concepts in testing, and verification / validation of microelectronic circuits and systems. Major topics include, but are not limited to:

Analog, M-S & RF Test
Automatic Test Generation
ATE Architecture & SW
Board & System Test
Built-In Self-Test (BIST)
Current Based Test
Defect Tolerance
Delay & Performance Test
Design for Testability (DFT)
Design Verification/Validation
Diagnosis and Debug
Embedded System Test
Embedded Test Methods
Fault Modeling and Simulation
Infrastructure IP
MEMS Test
Memory Test and Repair
Microprocessor Test
Multi-Chip Module Test
Nanometer Technologies Test
On-Line Test
Power Issues in Test
Self-Repair & Fault Tolerance
System-on-Chip (SOC) Test
System-in-Package Test
Test Resource Partitioning
Thermal Test
Test Data Compression
Test of High-Speed I/O
Test Quality and Reliability
Test Resource Partitioning
Transients and Soft Errors
Yield Analysis & Optimization

Author Information

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The VTS 2008 website is open for submissions:

http://www.tttc-vts.org/public_html/new/2008/submissions.php

The VTS Program Committee invites original, unpublished paper submissions for VTS 2008. Paper submissions should be complete manuscripts, up to eight pages (inclusive of figures, tables, and bibliography) in a standard IEEE two-column format; papers exceeding the page limit will be returned without review. Authors should clearly explain the significance of the work, highlight novel features, and describe its current status. On the title page, please include: author name(s) and affiliation(s), and the mailing address, phone number, fax number, and e-mail address of the contact author. A 50-word abstract and five keywords identifying the topic area are also required.

Proposals for the Innovative Practices track, and Special Sessions are also invited. The innovative practices track will highlight cutting-edge challenges faced by test practitioners, and innovative solutions employed to address them. Special sessions can include panels, embedded tutorials, or hot topic presentations. Innovative practices track and special session proposals should include a title, name and contact information of the session organizer(s), a 150-to-200 word abstract, and a list of prospective participants.

All submissions are to be made electronically through the VTS website. The deadline for regular paper submission is November 5, 2007 . Detailed instructions for submissions are to be found at the conference website http://www.tttc-vts.org. Authors will be notified of the disposition of their papers by 21st December 2007. A submission will be considered as evidence that, upon acceptance, the author(s) will present the paper at the symposium, and will submit a final camera-ready version of the paper for inclusion in the proceedings. In the case of innovative practice and special sessions, the organizers commit to submit a session title, abstract, and list of participants for inclusion in the symposium proceedings and program.

VTS 2008 will present a Best Paper Award, a Best Panel Award, and a Best IP Track Session Award based on the evaluations of reviewers, attendees, and an invited panel of judges.

TTTC Test Technology Educational Program (TTEP) tutorials on emerging test technology topics will be offered during VTS 2008. Tutorial proposals should be submitted according to TTEP 2008 submission deadlines (http://tab.computer.org/tttc/teg/ttep).

VTS08 Call-for-Paper is at: http://www.tttc-vts.org/public_html/new/2008/cfp.pdf

Deadlines

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VTS08 Submission Deadlines:
Regular paper full version: Nov 5, 2007
Innovative Practice Tracks proposals: Dec 31, 2007
Specal Sessions proposals: Dec 31, 2007

All submissions are to be made electronically through the VTS website.

Additional Information Contacts

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Regular Paper proposal, please contact VTS08 Program Chairs:
Peter Maxwell pmaxwell@micron.com
Cecilia Metra cmetra@deis.unibo.it

Innovative Practice Tracks proposal, please contact VTS08 IP Tracks Chairs:
Hatayama Kazumi hatayama.kazumi@starc.or.jp
Subhasish Mitra smitra@dodge.stanford.edu

Specal Sessions proposal, please contact VTS08 Special Sessions Chairs:
Lorena Anghel Lorena.Anghel@imag.fr
C.P. Ravikumar ravikumar@ti.com

For general information:

GENERAL CHAIR

Alex Orailoglu
University of California, San Diego
Dept. of Computer Science and Eng.
9500 Gilman Drive, Mail Code 0114
La Jolla, CA 92093-0114, USA
T: +1-858-534-0914
E: alex@cs.ucsd.edu

For Regular Paper submission related information:

PROGRAM CO-CHAIR
Peter Maxwell
Micron Technology
3080 North 1st Street, MS 65-300
San Jose, CA 95134, USA
T: +1 408 834 1643
F: +1 408 834 1223
E: pmaxwell@micron.com

PROGRAM CO-CHAIR
Cecilia Metra
ARCES - University of Bologna
Viale Risorgimento 2
40136 Bologna, Italy
T: + 39 051 209 3038
F: + 39 051 209 3073
E: cmetra@deis.unibo.it

Committees

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General Chair
A. Orailoglu - UC San Diego

Program Chair
P. Maxwell - Micron
C. Metra - U Bologna

Past Chair
P. Prinetto – Polit di Torino

Vice-General Co-Chairs
S. M. Reddy – U Iowa
H.-J. Wunderlich – U Stuttgart

Vice-Program Chair
M. Renovell – LIRMM

New Topics
B. Courtois – TIMA

Special Sessions
L. Anghel – TIMA
C.P. Ravikumar – Texas Instr

Innovative Practices Track
K. Hatayama – STARC
S. Mitra – Stanford U

Registration
C. Thibeault–E Tech Sup Montreal

Publicity
C.-H. Chiang – Alcatel-Lucent

Publications
S. Ravi – Texas Instr

Audio/Visual
S. Hellebrand – U Paderborn

Finance
M. Abadir – Freescale

Local Arrangements
I. Harris – UC Irvine

Latin America Liaison
L. Carro – UFRGS

North America Liaison
R. Kapur – Synopsys

Asia & Pacific Liaison
Y. Sato – Hitachi

Eastern Europe Liaison
R. Ubar – Tallinn U

Western Europe Liaison
Z. Peng – Linkoping U

Ex-Officio
Y. Zorian – Virage Logic

Program Committee (to include):
J. A. Abraham – UT Austin
V. D. Agrawal – Auburn U
D. Appello – STMicroelectronics
K. Arabi – PMC-Sierra
B. Becker – U Freiburg
C.J. Clark – Intellitech
B. Cory – NVIDIA
R. Galivanche – Intel
P. Girard - LIRMM
D. Gizopoulos – U Piraeus
S. Gupta - USC
I. Hartanto – Xilinx
B. Kaminska – Pultronics
A. Khoche – Verigy
H. Konuk – Broadcom
C. Landrault – LIRMM
X. Li – Chinese Academy of Sciences
F. Lombardi – Northeastern U
Y. Makris – Yale U
E.J. Marinissen – NXP
E.J. McCluskey – Stanford U
L. Milor – Georgia Tech
P. Muhmenthaler – Infineon
Z. Navabi – Northeastern U
S. Ozev – Duke U
J. Plusquellic – UMBC
A. Raghunathan – NEC
J. Rajski – Mentor Graphics
S. Shoukourian – Virage Logic
M. Soma – U Washington
S. Sunter – LogicVision
J. Tyszer – Poznan U
C. -W. Wu – Nat Tsing Hua U

Steering Committee:
J. Figueras – U Pol Catalunya
A. Ivanov – UBC
M. Nicolaidis – TIMA
A. Singh – Auburn U
P. Varma – Blue Pearl
Y. Zorian – Virage Logic

For more information, visit us on the web at: http://www.tttc-vts.org

The 26th IEEE VLSI TEST SYMPOSIUM (VTS 2008) is sponsored by the Institute of Electrical and Electronics Engineers (IEEE) Computer Society's Test Technology Technical Council (TTTC).

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	26th IEEE VLSI TEST SYMPOSIUM (VTS 2008) May 4th - 8th, 2008 San Diego, California USA http://www.tttc-vts.org